For many applications, read-only memory cell arrangements with electrically writeable and electrically erasable read-only memory cells in silicon technology, known as flash EEPROM, are required. These flash EEPROM arrangements maintain the stored data even without a voltage supply.
Technologically, these memory cells are mostly realized by an MOS transistor comprising in the channel region a first dielectric, a floating gate, a second dielectric and a control gate. If a charge is stored on the floating gate, this influences the threshold voltage of the MOS transistor. In such a memory cell arrangement, the state charge on the floating gate" is allocated to a second logical value. The information is written into the memory cells via a Fowler-Nordheim tunnel current, through which electrons are injected onto the floating gate. The information is erased by a tunnel current in the opposed direction through the first dielectric.
The MOS transistors are formed in memory cell arrangements of this sort as planar MOS transistors, and are arranged in a planar cell architecture. In this way, the theoretically minimum surface requirement of a memory cell is 4F.sup.2, whereby F is the smallest manufacturable structural size in the respective technology. Flash EEPROM arrangements of this type are currently offered for data quantities of a maximum of 64 Mbit.
In EP 0 673 070 A2, an EEPROM arrangement was proposed in which planar MOS transistors in the sense of a NAND logic are connected in series. Source/drain regions connected with one another of adjacent MOS transistors are thus designed as a common doped region. The EEPROM arrangement is realized in a semiconductor substrate that is provided on a main surface with strip-shaped trenches running in parallel. The MOS transistors connected in series are respectively arranged on the bottom of the trenches or between adjacent trenches on the main surface of the substrate. Adjacent rows of MOS transistors are insulated against one another by the side wall of the trenches, and insulating spacers are provided on the side wall of the trenches. The floating gates of the MOS transistors arranged on the bottom of the trench respectively fill out the trench width. Due to the insulating spacers arranged on the side walls of the trenches, the width of the floating gate at the boundary surface to the second dielectric is slightly larger than at the boundary surface to the first dielectric. The known EEPROM arrangement thus comprises a coupling ratio close to one. The term coupling ratio designates the quotient of the capacitance between the control gate and the floating gate and the capacitance between the floating gate and the channel region.